1. Field of the Invention
The present invention is directed to a random-access memory in integrated circuit form with an accelerated reading cycle. This acceleration is due to a novel organization of the reading operations. The same principle can also be applied to writing. The invention can be applied more particularly in the field of EPROM type memories or in that of EEPROM type memories wherein the memory cell has a floating-gate transistor as its storage element. In these fields, it is particularly well-suited to flash EPROM type memories.
2. Discussion of the Related Art
EPROM memories are non-volatile memories wherein the writing is done electrically, cell by cell, but for which the erasure is total: by ultraviolet radiation. EEPROM memories are also non-volatile memories but their writing and erasure are electrical. The erasure however is done by blocks of memory cells. The flash EPROM memories are non-volatile memories for which the writing and erasure are electrical with, however, particular constraints of use. For these memories, the invention makes a promising contribution because, apart from the acceleration obtained in reading, it restricts the effects of these constraints.
The memory cells of a memory are organized in matrix form at the intersections of rows and columns: the rows are called bit lines and the columns are word lines. To gain access to the information contained in a memory cell, decoders are used to select a bit line and a word line characteristic of the memory cell to be read. The selection of a memory cell is designed to connect it to a detection circuit, which is generally a current sensing circuit. The memory cell constituted by the floating gate transistor then behaves, depending on its programmed state, like a low-value resistor or like an open circuit. If it is a resistor, the bit line to which it belongs is, at the time of the selection, connected to the ground of the circuit of the memory. Thus, a discharge current may flow in the bit line. However, if it is an open circuit, a voltage applied beforehand to the bit line is kept. A current sensor detects or does not detect the passage of discharge current. Consequently, a static electrical state, the electrical state programmed in the memory cell, has been converted into a dynamic electrical state: namely a state that varies in time. This change in state is then used in the different circuits connected to the memory.
As described, the process requires the precharging of the bit line at a certain voltage, before the selection of the memory cell concerned by the bit line. The current sensor circuit is connected to the bit line at least at the end of this precharging operation. As soon as the concerned word line is activated, the phenomenon of short circuit or open circuit occurs and current flows or does not flow through the current sensor. Since the current sensor is thus connected beforehand to the bit line, methods for precharging the bit line have been developed wherein the precharging circuit of the bit line is integrated with the current sensor.
Before the precharging, in the case of the EEPROM memories, it is necessary however to reset the bit lines and word lines at zero so that the precharging is done properly, notably so that firstly it starts and secondly the precharging voltages of the different bit lines are the same. In the case of the EPROM memories, the word lines must be grounded or taken to a voltage lower than the reading voltage so as not to affect the cells. Before the precharging in this case, the bit lines are taken to high impedance: they are disconnected from the sensing circuits. In practice, all the connections and impositions of voltage depend firstly on the technology chosen (EPROM-EEPROM) and secondly on the embodiment of the reading circuits.
The problems encountered with memories of this type are generally related to their speed. For example, for the reading, the operations of resetting the bit lines, precharging the bit lines, reading and read storage should take less time than the nominal period of time stated for a range of circuits. It is becoming increasingly difficult to meet this speed requirement because the sizes of the memories are tending to increase. Consequently, these bit lines and word lines are longer and the period of propagation of the signals becomes great. This means that it is no longer possible to comply with the nominal period of time. To accelerate these operations, the French patent application No. 89, filed on 2 Oct. 1989, and published under No. 2 652 672, has already provided for making the bit line precharging operation faster. In a French patent application No. 92 09197, filed on 24 Jul. 1992, a method has been devised for precharging also an output amplifier so that the build-up time of this amplifier does not entail being subjected to a delay at transmission.